An 8.5 ps Resolution, Cyclic Vernier TDC Using a Stage-Gated Ring Oscillator and DWA-Based Dynamic Element Matching in 28 nm CMOS

Herein, we present a cyclic Vernier time-to-digital converter (TDC) using a stage-gated ring oscillator (SGRO) and data-weighted averaging (DWA) dynamic element matching (DEM). Using the phase-preserving characteristic of SGRO, DEM is realized using simple enable switches. DWA is achieved by storing the SGRO's previous state and using it as the beginning state of the next conversion. This approach achieves cyclic selection of signal propagation paths in SGRO, and the systematic mismatch is averaged out through multiple conversions. DWA achieves the first-order mismatch correction, further improving linearity. Circuit techniques are presented to achieve accurate measurement by removing errors occurring in multiphase time-domain processing. A TDC fabricated with a 28-nm CMOS process is realized in a compact area of 0.0056 mm(2). Measurements show that the TDC achieves an 8.5-ps resolution and an 11-bit dynamic range (DR). Full range linearity measurement shows a maximum differential nonlinearity (DNL) of 0.3 LSB and integral nonlinearity (INL) of 2.3 LSB. The power consumption is only 0.198 mW at a 15-MS/s conversion rate, resulting in a favorable figure of merit (FoM) of 0.021 pJ/conversion step. The results show the effectiveness of the proposed TDC for improved linearity and resolution.