A General Common-Bus Architecture for Multiple-Interface Power Hardware-in-the-Loop Studies

Power hardware-in-the-loop provides a safe and relatively small test platform to a wide range of power devices. The limits of the technique are constantly being pushed, with faster real-time simulations, higher bandwidth amplifiers, and more complex systems. A particular way that the complexity of the system can be increased is through the inclusion of multiple power hardware-in-the-loop interfaces between the simulated system and the physical devices. The intricacy of multiple interfaces increases the chances of inaccuracy and instability of the system however, as each new interface can potentially add unwanted distortions. Therefore, it is important that the behavior of the system is well understood. In this paper, an approach to analyze a general common-bus architecture for multiple-interface power hardware-in-the-loop simulations is proposed. This approach allows for an easy and quick method to obtain analytical solutions to the stability and accuracy of a commonly found configuration in PHIL simulations.