Modified Baugh Wooley Multiplier using Low Power Compressors

Multipliers are basic building blocks of many digital systems such as digital signal processing application, microprocessor, digital communication etc. Multipliers possess huge power and delay. So, it is inevitable to reduce the power consumption and delay of multipliers in order to get high performance digital system. Modified Baugh Wooley Multiplier is a widely used 2’s complement multiplier which multiplies negative as well as positive numbers efficiently. Modified Baugh Wooley multipliers are very efficient in handling sign bits. In this paper a 16-bit Modified Baugh Wooley Multiplier is presented. The proposed circuit is designed using low power compressors and full adders and modified Ripple Carry Adder and simulated in Cadence Virtuoso using gpdk 45nm technology. From the simulation it is observed that the design consumes less power and less delay as compared to conventional circuits. The transistor count of the design is also less.