(Invited) Progress in Buried Grid Technology for Improvements in on-Resistance of High Voltage SiC Devices

Silicon Carbide (SiC) is regarded as the material of choice for high voltage (>1kV) power devices due to its material properties, mature fabrication technology, and availability of 150mm diameter wafer material. SiC power devices like Schottky barrier diodes (SBDs) and MOSFETs with voltage ratings of 1700V and current handling capabilities of 50A and more are commercially available from several vendors. Commercial SiC SBDs are based on the merged p-n junction and Schottky (MPS) concept or the junction barrier controlled Schottky (JBS) concept. Commercial MOSFETs utilize the VDMOS concept having a vertical device design with lateral channel and the UMOS concept with vertical channel at trench sidewalls. Common for these device concepts is that the electric field at device areas like Schottky contacts and MOS interfaces is relatively high and limits often the device performance. This leads to that the full potential of SiC devices cannot be realized. For example, in planar surface p-grid JBS diode structures the protection of the Schottky areas from high electric field is not sufficient and result in high leakage currents limiting the SOA in terms of junction and operation temperature. In addition, the edge termination is realized at the top surface of the SiC material and has to be carefully designed to not exceed the limitations of passivation and packaging materials. Buried grid technology is suggested to decrease the electric field at field sensitive device areas and to move areas of high electric field into the SiC bulk. It was demonstrated for SiC JBS diodes that buried grid technology gives more than three orders of magnitude lower leakage currents even at high temperature operation due to the superior shielding effect. The drawback is that the introduction of the buried grid increases the total resistance and therefore increases the forward voltage drop at rated current and the conduction losses. In this paper, we review our work on improving the on-state characteristics of buried grid SiC devices. The work is mainly done for buried grid JBS-diodes (BG-JBS), but can be applied also to buried grid MOSFETs (BG-MOSFET). For the BG-SiC devices, a p-grid is fabricated either by aluminum implantation followed by high temperature anneal or trench etching with subsequent epitaxial re-growth and planarization to fill up etched trenches with p-type material. As a final step, the p-grid is buried by another re-growth step of a thin n-layer. The epitaxial grid approach is done with Ascatron’s 3D-SiC core technology based on embedded epitaxial growth techniques, replacing high dose ion implantation at elevated temperatures and high temperature anneal by epitaxial growth in trenches. For cost-effective fabrication, this process should be performed in multi-wafer reactors. For devices with blocking capability of up to 1700V, we typically employ floating ring type edge termination formed simultaneously with the active area p-grid. For higher voltages than 1700V we suggest to use a JTE type edge termination formed by ion implantation in the same layer as the p-grid. Hence, the edge termination is also buried in the SiC bulk. By carefully designing the drift and re-growth layers as well as the epitaxial or implanted p-grid, the fabrication process can be optimized in terms of trade-off between current handling capability in forward and blocking behavior and leakage current in reverse. In addition, the size and spacing of the p-areas are critical parameters to optimize the BG-SiC device performance to realize maximum current handling capability at forward voltage similar or below surface grid devices and minimum leakage current especially for high temperature operation. To reduce the forward voltage, we employed relatively high n-doping in the channel regions between the p-islands and optimized the drift and re-grown top layer doping. Due to the superior material quality, epitaxial grown BG-structures result in increased bipolar injection at high current densities and thus give improved surge current capabilities. In addition, epitaxial p-n junctions show lower leakage currents than implanted ones.