(Invited) Processing Technologies for Advanced Ge Devices

With proceeding CMOS device scaling, process technologies become more and more challenging as the allowable thermal budget for device processing continuously reduces. This is especially the case during epitaxial growth, where a reduction of the thermal budget is required for a number of potential reasons (e.g. to avoid uncontrolled layer relaxation of strained layers, surface reflow of narrow FIN structures, as well as doping diffusion and material intermixing). Different aspects become even more challenging when Ge is used as a high-mobility channel material and when the device concept moves from a FINFET design to a nanowire FET design (also called Gate All Around FET). In this presentation we will address some of the challenges involved with the integration of high mobility Group IV materials in these advanced device structures. Recently, we described the issue of Ge thermal instability against surface migration during selective epitaxial growth (SEG) of Ge by means of Chemical Vapor Deposition (CVD) in extremely narrow channels isolated by SiO2 [1]. Above a critical growth temperature filling of narrow channels is prohibited by Ge migration over the surface, due to the high Ge chemical potential in such narrow channels. The design of the FIN structure affects the maximal allowable growth temperature. This is critical as maintaining material quality sets a lower limit on the growth temperature [2]. Similar limitations need to be taken into account for the SEG of compressive strained Ge on top of a SiGe strain relaxed buffer (SRB). In addition, the reduced STI depth as used for high density FINs restricts the thickness of the SRB layer. The use of a V-shaped Si recess, combined with the deposition of a Ge-rich SiGe seed layer before the SRB growth, allows to reduce the Si0.3Ge0.7SRB thickness down to ~55nm while maintaining full strain relaxation (Fig. 1a). To investigate the strain state in more detail, reciprocal space maps (RSMs) were performed both along (longitudinal) and across (transverse) the fins [3,4]. From the RSMs, it is clear that the SiGe SRBs are relaxed with respect to the Si substrate. The Ge cap layer is uniaxially strained along the fins, with some relaxation occurring across the fins (Fig. 1b,c). An ultrathin Si layer is typically used to passivate the Ge surface in the high k gate module. The risk for Ge surface reflow, which in turn would lead to a (partial) relaxation of the strained Ge layer, sets the need to use high order Si-precursors such as Si3H8 and Si4H10to enable epitaxial growth at the required extremely low Si growth temperatures (< 350 °C) [4,5]. Horizontal gate all around (GAA) FETs are being considered a next logical step in scaling of Fin FETs for the 7 and 5 nm technological nodes. Their production promises little deviation from a standard Fin FETs processing flow and dramatic improvement of electro-static properties. In order to produce GAA FETs a stacking of two materials, typically Si/SiGe or SiGe/Ge, is used. An ultimate scaling of this technology assumes use of either Si or Ge and SiGe with high Ge contents close to 50%. Growth of such Si/SiGe or Ge/SiGe stacks with a large lattice mismatch is challenging since it is can only be done at low temperatures to avoid strain relaxation which would go together with defect incorporation. The use of higher order precursors allows to deposit fully strained and defect free Si/Si0.6Ge0.4 and Ge/Si 0.35 Ge 0.65 stacks with sharp interfaces between layers (Fig. 2), which are the most important requirements for GAA production. It enables us to demonstrate GAA FETs made of vertically stacked horizontal nanowires with excellent short-channel characteristics [8]. Acknowledgements: The imec core CMOS program members, European Commission, local authorities and the imec pilot line are acknowledged for their support. Epi layers are grown in EpsilonTM3200 and IntrepidTMXP systems from ASM. Air Liquide Advanced Materials is acknowledged for providing advanced precursor gases and Bruker Semiconductor Division for their kind support in XRD characterization of high mobility materials implemented in complex device architectures. References: [1] G. Wang et al, Journal of Applied Physics 108, 123517 (2010) [2] R. Loo et al. ICSI-9, 2015, p. 21 [3] P. Ryan et al. International Conference on Frontiers of Characterization and Metrology for Nanoelectronics (2015) [4] J. Mitard et al. accepted for VLSI 2016 [5] H. Arimura et al, IEDM 2015, p. 588 [6] A. Hikavyy et al. ICSI-9, 2015, p. 209 [7] A. Hikavyy et al. to be presented at ISTDM 2016 [8] H. Mertens et al. accepted for VLSI 2016 Figure 1