Efficient implementation of Montgomery modular multiplier on FPGA

Recent developments in embedded devices have enhanced the demand for systems using compact cryptographic modules. Modular multiplication with large modulus is a central procedure in many public-key cryptosystems. This work describes a creative structure of an FPGA hardware architecture to compute the modular multiplication of two integers. The proposed design has enhanced the hardware structure of Montgomery Modular Multiplier (MMM) in a more efficient way to increase the performance and decrease the area cost. The proposed design is coded in VHDL, and implemented in real-time on the Nexys-3 board. The synthesis results of implementing the proposed 256-bit and 1024-bit modular multiplier on Virtex-6 FPGA have a computation time 1.79 mu s and 20.53 mu s, occupies 1104 LUTs and 4450 LUTs, and runs at 143.82 MHz and 49 MHz, respectively. Compared to other related FPGA implementations, the proposed design uses less FPGA resources with better efficiency and lower Area Time per bit-length (AT/b).