Area And Power-Efficient Capacitively-Coupled Chopper Instrumentation Amplifiers In 28 Nm Cmos For Multi-Channel Biosensing Applications

This paper presents two designs of a capacitively-coupled chopper instrumentation amplifier (CCIA) successfully implemented in 28 nm CMOS for biopotential sensing applications. The first design is a compact CCIA using offset-blocking for chopping ripple reduction, DC servo loop (DSL) for electrode offset (VEOS) suppression, and a high pass filter (HPF) for handling common-mode (CM) artifacts. An inverter-based self-biased input stage is used for noise and power efficiency. The two gain stages of the CCIA achieve a low-frequency open-loop gain > 80 dB. Realized in an area of 0.05 mm(2), the CCIA handles V-EOS up to 50 mV and tolerates CM artifacts up to 1.5 V-pp. The CCIA achieves a mid-band gain of 39.5 dB with a 1 kHz bandwidth by consuming 1 mu W. The integrated input-referred noise (IRN) over 200 Hz bandwidth is 2.15 mu V-rms. The second design presents a dual-channel CCIA (DCCIA) using an orthogonal frequency chopping for multi-sensor array applications. An inverter-based input stage is used for noise efficiency. The measured results show that the DCCIA achieves a low-frequency gain of 39.5 dB with a 3-dB bandwidth up to 1 kHz by consuming 0.71 mu W per channel. The measured noise density is 136 nV/root Hz with an integrated noise of 2.67 mu V-rms over 200 Hz bandwidth. The DCCIA suppresses VEOS up to 50 mV using the DSL. Realized in a compact area of 0.04 mm2 per channel, an excellent gain matching error of 0.29% is achieved with the crosstalk higher than 58 dB between the channels. Thiswork is a measured report on the instrumentation amplifier using, to the best of the authors' knowledge, one of the smallest CMOS process nodes.