Fundamental Power Limits Of Sar And Delta Sigma Analog-To-Digital Converters

This work aims at estimating and comparing the power limits of Delta Sigma and charge-redistribution successive-approximation register (CR-SAR) analog-to-digital converters (ADCs), in order to identify which topology is the most power-efficient for a target resolution. A power consumption model for mismatch-limited SAR ADCs and for discrete-time (DT) Delta Sigma modulators is presented and validated against experimental data. SAR ADCs are found to be the best choice for low-to-medium resolutions, up to roughly 80 dB of dynamic range (DR). At high resolutions, on the other hand, Delta Sigma modulators become more power-efficient. This is due to the intrinsic robustness of the Delta Sigma modulation principle against circuit imperfections and non-idealities. Furthermore, a comparison of the area occupation of such topologies reveals that, at high resolutions and for a given dynamic range, Delta Sigma ADCs result more area-efficient as well.