Graphene And 2d Crystal Tunnel Transistors

Transistors in the traditional field effect geometry operate by the injection of mobile carriers – electrons or holes – from a source reservoir to the drain reservoir through a conducting channel region. The carriers enter the channel region by surmounting an electrostatic potential barrier. The gate electrode controls the height of this barrier capacitively. The carriers in the source reservoir are in thermal equilibrium with the source contact. This means that the carriers, say electrons, are distributed in energy in the conduction band according to the Fermi–Dirac distribution f(E = 1/1[1+exp((E − EF)/kT)]. The Maxwell–Boltzmann approximation f(E) ~ exp[− E/kT] of the Fermi–Dirac distribution for large energies represents the high-energy tail of the distribution. There are electrons in this tail with energy higher than the potential barrier; the gate cannot stop them from being injected into the channel. This leads to a sub-threshold “leakage” drain current ID ~ exp[qVGS / kT], which leads to the well-known sub-threshold slope (S) requirement of S ~ (kT / q)ln10 ~ 60 mV/dec change of current. Methods to make the SS steeper than the 300 K value of 60 mV/dec value are expected to substantially lower the power dissipation in digital logic and computation [1, 2]. The methods must explore novel mechanisms of charge transport, or of electrostatic gating. This chapter focuses on transport.