Limits Of Gate Dielectrics Scaling

This chapter discusses limits of gate dielectric scaling for advanced metal oxide semiconductor field effect transistor (MOSFET). We will review details of hafnium oxide (HfO2) gate oxide and how HfO2 can be modified to hafnium oxynitrides (HfON) and hafnium lanthanum oxynitrides (HfLaON) to increase dielectric constant for continuous equivalent oxide thickness (EOT) scaling. Bilayer hafnium oxide/titanium oxide (HfO2/TiO2) as a higher ‘k’ dielectric option for FinFET gate length (Lg) scaling is discussed. Interfacial layer (IL) scaling technologies for overall EOT scaling are also covered in this chapter. Ab-initio modeling results to evaluate ternary and quaternary gate oxide for higher ‘k’ dielectrics options, and effective metal work functions calculations to optimize and develop new metal gates are discussed. New gate dielectric reliability failure mechanisms due to three dimensional natures of FinFET devices are reviewed. Thermal oxide equivalent quality deposited silicon dioxide (SiO2) using atomic layer deposition (ALD) with post-treatments (e.g., plasma nitridation and anneals) as a high voltage input/output (I/O) gate oxide with silicon-germanium channel (SiGe) results are shown. Finally, we give a brief overview of silicon germanium pFET channel material as a gate dielectric scaling knob, and how it can enable continued EOT scaling without reliability degradation.