On-Line Testing And Recovery Of Systems With Dynamic Partial Reconfiguration

The FPGA devices are increasingly being used in mission critical systems like security systems, banking systems, and avionics. The errors induced by high-energy radiation, also known as Single Event Upsets (SEUs), corrupt the configuration memory of the FPGA device and are a major concern for the system reliability and dependability. For this, error mitigation techniques like triple module redundancy and ECC codes are commonly employed techniques. However error mitigation techniques do not recover the system. The fault-free system can be recovered using reconfiguration of the FPGA device. Previous recovery methods employ processor cores as a reconfiguration controller consuming notable amount of device resources and introducing additional error detection and recovery latency. In this paper a low area overhead error recovery mechanism for SRAM based FPGA systems is presented. The error recovery mechanism is implemented as a state machine. The reliability of the developed solution was experimentally evaluated by fault emulation environment.