Copper Interconnect Technology In Semiconductor Manufacturing

CMOS integrated circuit technology with Cu interconnections first reached the point of "qualified for manufacturing" at the end of 2Q98, and subsequently "qualified for shipping" (from a high-volume line) several months later. By the date of this conference, hundreds of thousands of 6-level "copper-chip" microprocessor modules were shipped, and a new generation high-end Server was announced with Cu-interconnected microprocessors' (up to 14 in parallel) and support chips. This technology has remained on track for a full range of logic chips, from PC2 to high-end server CPUs(1), from ASICs to Foundry offerings, and the next generation CMOS parts including embedded DRAM(3), and those on SOI substrates(4,5). To manufacture chips with Cu interconnects, we are enabled by bringing in several electrochemical and chemical processes, including Cu electrodeposition and chemical-mechanical polishing, coupled with the dual-Damascene patterning scheme. At the same time, it is notable that only one new type of tool, an automated wafer Cu electroplater, was required to make the transition from Al- to Cu-based interconnect manufacturing, Cu interconnect demonstrations have been shown in the Literature for years, but behind the scenes, significant process development has been required to successfully bring such a revolutionary technology to product yield levels, and at the same time maintain performance, reliability, and quality standards. Here we show data that illustrate the successful implementation of this new technology in manufacturing.