A Novel Incremental Algorithm For Non-Slicing Floorplan With Low Time Complexity

Incremental modification and optimization is very important in VLSI physical design. In this paper, we present a novel incremental algorithm for non-slicing floorplan based on Corner Block List representation with low time complexity. To implement incremental floorplan, constraint graphs are produced simultaneously with the packing process of transform CBL to its corresponding floorplan, which takes O(n) time. Based on the critical path and the accumulated slack distances, we can determine the balance point of insertion and do a series of operations incrementally, such as deleting, inserting, resizing modules quickly. And the time complexity of incremental modification process is O(n). The experimental results show that wirelength of all incremental modifications are decrease compared with the initial floorplan. The total wirelength of all incremental floorplans have been improved from 0.1% to 9.0%. And the CPU time of incremental modifications are so small that most of them are within micro second. The experimental results of MCNC benchmarks prove the effectiveness of our algorithm.