A Small-Footprint Quasi-Passive 1st Order Sigma Delta Modulator

Discrete-time Sigma Delta generally rely on switched capacitor implementations that require operational amplifiers to implement the integrators. For ultra-deep submicron processes, the limited intrinsic gain of the transistor hinders the design of operational amplifiers. This paper proposes a topology for Sigma Delta modulators that employs a low-power quasi-passive integrator. The input voltage is converted into the charge domain by a transconductor-based front-end. The integration process is implemented with MOS capacitors instead of linear capacitors, which allows the reduction of charge leakage. While this design targets relatively low resolutions, due to the nonlinear nature of the passive integration, the absence of operational amplifiers enables the topology to fit in a very small area. The topology is validated by simulations with the design of a 1st order Sigma Delta modulator. The circuit is designed in a 0.13 mu m technology, fits in 40 x 60 um(2), performs at 100 MSps with 51.34 dB of SNDR and consumes 0.08 mW.