On the Suitability of Read only Memory for FPGA-Based CAM Emulation Using Partial Reconfiguration.

Content-addressable memory (CAM) is a high-speed searching memory that provides the address of the input search key in one clock cycle. Traditional implementations of large CAMs on FPGAs with updatable memory elements are resource intensive requiring bigger and more expensive chips. Additional circuitry required for updating the CAM content is a major contributor to this which also impacts the overall clock performance of the circuit thus hampering the system throughput. To reduce the resource requirement, we investigate CAM implementation using read only memories (ROMs) and using partial reconfiguration (PR) to update their contents. Using a high-speed reconfiguration controller and bitstream compression, the reconfiguration overhead due to PR is offsetted. The results show 10% and 200% improvement in hardware resources and speed, respectively, compared to the state-of-the-art available FPGA-based TCAMs.