A Temperature-Compensated 57 Ppm/Degrees C 10mhz, 2.4 Mu W Stacked Ring Oscillator

Ring oscillators are one of the simplest, smallest and most energy-e fficient topologies when it comes to clock generation. Being implemented using a chain of digital inverters, their oscillation frequency can be set by the inverters count in the chain and the delay of each inverter. This is an advantage when considering the simplicity and size, however, it is also the cause for high frequency variation with temperature. In this paper we propose an ultra-low power oscillator circuit that exploits a stack of small ring oscillators for supply current reuse and injection locking, which provides phase noise improvement. Frequency stability is achieved through a feedback loop that relies on a frequency-to-voltage converter with improved linearity and reduced temperature sensitivity based on MOS capacitors. Simulation results show that the oscillation frequency changes +/-0.4% from 0 to 70 degrees C (57 ppm /degrees C) while consuming 2.4 mu W at 10 MHz, with a phase noise of -88.9 dBc /Hz at 100 kHz o ffset.