Charge-trapping memory device based on a heterostructure of MoS 2 and CrPS 4

omically thin two-dimensional (2D) materials have emerged as promising candidates for flexible and transparent electronic applications. Here, we introduce non-volatile charge trapping memory devices, based on the 2D heterostructure field-effect transistor consisting of a few-layer MoS 2 channel and CrPS 4 charge-trapping gate stack. Clockwise hysteresis behaviors in transfer curves measured at room temperature show strong dependence on the thickness of CrPS 4 , which are attributed to charge trapping at trap sites in the CrPS 4 layers. Our heterostructure memory device with 75 nm-thick CrPS 4 layer exhibits both large memory windows up to 100 V and a high on/off current ratio (3 × 10 5 ) with good endurance during 625 cycles because of excellent trapping ability of trap sites in the CrPS 4 . Especially, the memory window size can be effectively tuned from 7.6 to 100 V by changing the sweep range of gate voltage. Such high performances of the charge-trapping memory device with a simple heterostructure provide a promising route towards next-generation memory devices utilizing 2D materials.