Excellent Mechanical Durability of In‐Folding Stress of Poly‐Si Thin‐Film Transistor on Plastic Substrate Compared with Out‐Folding: Generation of Gate Leakage Currents in Flexible Poly‐Si Thin‐Film Transistor by Out‐Folding and Bias‐Temperature Stress

The effect of electro-thermal stress on the electrical performance of flexible, low-temperature polysilicon (LTPS) thin-film transistors (TFTs) after mechanical-folding stress aiming to improve the reliability of foldable display backplanes is studied (I-G). Herein, for the first time, the significant increase of gate leakage currents upon the negative bias temperature stress (NBTS) or positive bias temperature stress (PBTS) after the out-folding test on excimer laser annealing (ELA) TFTs is reported. Out-folding stress increases the drain current, shifts the threshold voltage (Delta V-TH) by 2.4 V, and increases the subthreshold swing without affecting the (I-G). However, the Delta V-TH is 1.8 V upon NBTS, and the negative Delta V-TH is -4.7 V upon PBTS after out-folding stress along with a drastic increase in I-G. A thermal annealing at 250 degrees C for 10 h for the electro-thermal stressed TFTs after out-folding is performed, and initial electrical characteristics recovery is achieved; except the abruptly increased I-G. These results are correlated with charge trapping at the damaged grain boundary and (GI). A model with moisture/water molecule diffusion through the nanocracks generated by out-folding is proposed. The ionized charges (H+, OH-) captured at the nanocrack-induced trap sites in poly-Si and GI appear to be the origin of abnormal Delta V-TH and I-G.