A Proactive System for Voltage-Droop Mitigation in a 7-nm Hexagon™ Processor
IEEE Journal of Solid-State Circuits(2021)
摘要
A proactive clock-gating system (PCGS) in a 7-nm Qualcomm
®
Hexagon™ digital signal processor (DSP) improves performance or energy efficiency by reducing the magnitude of supply voltage ( V
DD
) droops. The PCGS integrates a digital power meter (DPM) to monitor the power per cycle based on microarchitectural events and a voltage-clock-gating (VCG) circuit with a power-delivery-network (PDN) model to predict the V
DD
response to DPM power changes. When the PDN model anticipates a potential V
DD
-droop violation, the VCG adapts the clock frequency ( F
CLK
) by gating the global clock to reduce the actual V
DD
-droop magnitude. Silicon measurements of the PCGS in the 7-nm DSP demonstrate a 10% higher F
CLK
or 5% lower V
DD
.
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关键词
Adaptive design,digital power meter (DPM),proactive design,variation-tolerant design,voltage droop,voltage prediction,voltage variation
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