Common Subexpression Convergence: A New Code Optimization for SIMT Processors

On SIMT processors, when threads in a warp diverge at a branch, the hardware scheduler serializes their execution, thereby resulting in reduced SIMT efficiency. We propose a new compiler optimization, Common Subexpression Convergence (CSC), that uses cross-block scheduling to ensure that expression trees that are common across diverged paths are moved to convergent regions and executed by more/all threads in parallel, thereby improving SIMT efficiency and execution time. Our optimization framework is based on a dynamic programming algorithm for finding maximally profitable common expression subgraphs. We also introduce a general approach to test the legality of our optimization based on the program dependence graph, and a heuristic-based cost model to decide when the optimization should be applied. We demonstrate the potential benefits of our approach through a preliminary hand-optimized evaluation using synthetic benchmarks and a BitonicSort example program.