Scalable Energy-Efficient Microarchitectures With Computational Error Tolerance Via Redundant Residue Number Systems

Due to high leakage current and threshold voltage, Dennard scaling has reached its limit on conventional semiconductor technology. Energy reduction at the transistor level by simply lowering supply voltage has proven to be infeasible for these devices (e.g., MOSFETs). Some recently proposed millivolt switch techniques aim to mitigate these issues, by maintaining a high on/off ratio of drain currents with a much lower supply voltage. However, $V_{dd}$ reduction is constrained by high intermittent error probabilities in millivolt switches. Energy-efficient microarchitectures that are computationally error-tolerant are therefore urgently needed. This article systematically leverages the error correction and checkpointing properties of Redundant Residue Number Systems (RRNS) by varying the number of non-redundant ( $n$ ) and redundant ( $r$ ) residues. The state-of-the-art of RRNS microarchitecture is confined to a fixed configuration point within such a ($n$n, $r$r)-RRNS design plane, as it supports single error correction alone. Being able to efficiently handle resilience in this ($n$n, $r$r)-RRNS plane significantly improves reliability, allowing further ${V_{dd}}$ reduction to save energy. To this end, first, we propose a scalable RRNS microarchitecture that simultaneously supports both, error-correction, as well as checkpointing with restart capabilities upon detecting uncorrectable errors. Second, we design a novel RRNS-based adaptive checkpointing&restart mechanisms that automatically guarantees reliability while minimizing the energy-delay product (EDP). To the best of our knowledge, these are the first set of checkpointing mechanisms targeting the RRNS infrastructure. Moreover, these mechanisms optimize the usage efficiency of memory capacity. Third, we systematically explore the RRNS design space to find the best ( $n$ , $r$ ) configuration point. For similar reliability when compared to a conventional binary core without computationally error-tolerant (runs at high $V_{dd}$ ), the proposed RRNS scalable microarchitecture reduces EDP by 53 percent on average for memory-intensive workloads and by 67 percent on average for non-memory-intensive workloads.