Experimental Validation of Process-Induced Variability Aware SPICE Simulation Platform for Sub-20 nm FinFET Technologies

We propose an experimentally validated physics-based process-induced variability (PIV) aware SPICE simulation framework-enabling the estimation of performance variation due to line-edge-roughness (LER), metal-gate-granularity (MGG), random-dopant-fluctuation (RDF), and oxide-thickness-variation (OTV) at sub-20 nm technology node devices. The framework utilizes LER, RDF, OTV, and MGG defining parameters such as fin-edge correlation coefficient (ρ), autocorrelation length (Λ), grain-size (GS), σ[EOT], etc. as the inputs, and produces I _d -V _g distribution of ensemble size 250 as an output. We have validated the framework against 14 nm FinFET experimental data for I _d -V _g trends as well as for the threshold-voltage (V _T ), ON-current (I _ON ), and subthreshold slope (SS) distributions for a range of device dimensions with a reasonably good match. The worst and the best case R square errors are 0.64 and 0.98, respectively, for the validation. The very nature of the proposed framework allows the designers to use it for a vast range of process technologies. Such models are of dual importance, as it enables a PIV aware prediction of circuit-level performance, and provides a platform to estimate PIV parameters efficiently, on-par with sophisticated structural characterization tools.