Low-If Interferometric Receiver Architecture For Massive-Iot Wireless Systems

A low-IF interferometric receiver architecture is proposed and implemented by eliminating two output ports of a conventional calibration-based six-port discriminator to further simplify the structure, and reduce its power consumption and cost in the context of massive internet-of-things (IoT) applications. The costly power-consuming high-speed analog-to-digital converters (ADCs) are thus reduced to a half. A theoretical analysis is presented to formulate an analytical procedure to benefit from a low intermediate frequency (IF) principle and regenerate baseband signals with two observations without any constraint on the input signal and error rate performance of a wireless node. A prototype is implemented in the 24 GHz frequency band and various modulations including QPSK, QAM-16 and QAM-32 have been successfully studied and demonstrated at 1 MSps of symbol rate with maximum error vector magnitude of 7.94 % rms free from a post-processing linearization and calibration. The maximum data rate is fundamentally limited by power detectors which are linked to their rise time.