A 24ghz Self-Calibrated Adpll-Based Fmcw Synthesizer With 0.01% Rms Frequency Error Under 3.2ghz Chirp Bandwidth And 320mhz/Mu S Slope

Frequency synthesizers are critical for millimeter-wave (mm-wave) frequency-modulated continuous-wave (FMCW) radars. Large-chirp-bandwidth ($BW_{chirp})$ sawtooth waveforms are required to be synthesized with fast slope and high-frequency linearity for accurate detection of targets or high-quality imaging. Fractional-N phase-locked loops (PLLs) with a two-point-modulation (TPM) scheme are widely used to synthesize fast high-linearity chirps [1] –[3]. However, for a wideband multi-bank digitally controlled oscillator (DCO), the intrinsic $1/ \\surd L\\mathrm{C}$ nonlinearity and the frequency discontinuity from overlaps between adjacent tuning bands introduce a significant gain mismatch between the two modulation paths of the TPM scheme and degrade the chirp linearity [3], [5]. To linearize the DCO tuning curve, a piecewise linear pre-distortion method is commonly used as shown in Fig. 32.5.1 [3]. In this method, the overlaps are mitigated by scaling every band with the same factor SC, which is based on the assumption that ratios of each DCO tuning band to the corresponding coarse frequency step remain the same. In practice, precise matching between these bands cannot be guaranteed. Each tuning band is then linearly fitted with its average gain $g_{i}$, but non-ideal residual frequency errors may still deteriorate the chirp linearity. As a DCO bandwidth increases, the mismatches and residual frequency errors tend to be more severe, making this method unsuitable for wideband FMCW synthesizers.