Effect of PECVD Gate SiO 2 Thickness on the Poly-Si/SiO 2 Interface in Low-Temperature Polycrystalline Silicon TFTs

This study investigates the effect of the gate SiO 2 thickness (80, 100, and 130 nm) deposited by plasma enhanced chemical vapor deposition on the interface and reliability characteristics of low-temperature polycrystalline silicon thin film transistors. Field effect mobility is significantly degraded as the gate oxide thickness decreases. The border trap density (N bt ) extracted from capacitance–voltage hysteresis exhibits no trend with respect to the gate oxide thickness, indicating that field effect mobility is not governed by N bt . The quantitative interface trap density (N it ) was obtained using a 3-terminal charge pumping method; results showed that N it decreased as the gate oxide thickness increased. However, it was observed that the threshold voltage (V th ) shift during negative bias temperature stress is worse in the thicker SiO 2 film, which has a low N it . After activation annealing, the amount of hydrogen in the gate oxide increased as the thickness of the insulator was raised. This in turn caused a larger shift in V th . To validate this mechanism, the amount of hydrogen with respect to the device depth was analyzed via secondary ion mass spectroscopy. It has been found that the presence of more hydrogen concentration in the SiO 2 film and the interface to the thicker SiO 2 results in more V th shifts under bias temperature stress.