High Noise Margin, Digital Logic Design Using Josephson Junction Field-Effect Transistors for Cryogenic Computing

As compute demands and their large energy costs continue to rise in the datacenter, it is imperative to identify low energy compute solutions. One approach is to investigate device schemes based on collective mode phenomena arising at low temperatures where power dissipation and switching voltage can be extremely low. Additionally, such devices could also have applications in quantum computing where such a low power logic/memory scheme could possibly be integrated onto the qubit plane, which is typically at ~10 mK temperature. Josephson Junction Field Effect Transistor (JJFET) is a promising candidate for low power operation with zero voltage drop across its drain-source terminals while operating in the superconducting regime. JJFET logic gate is typically realized as a n-type JJFET connected in a common-source configuration with a current source load. This results in high noise margin for logic-1 input but not for both logic-1 and 0. In this paper, we propose an overdamped region, n-type JJFET based digital logic using a cascaded common-source configuration-based design yielding high noise margin for both the logic inputs. DC noise margin sensitivity analysis is performed for the bias current and threshold voltage modulation. The noise margin can be further improved (approaches ideal inverter case) by cascading multiple common source stages yielding higher inverter gain.