A novel approach to fractional-N PLLs generating ultra-fast low-noise chirps for FMCW radar

This paper presents a novel approach to generate ultra-fast chirps for frequency-modulated continuous wave (FMCW) radar systems. A symmetric triangular frequency chirp is analyzed. A very large loop bandwidth could minimize the PLL settling time, but would result in a high phase noise and in large spurs. This work minimizes the settling times without using an excessive loop bandwidth. Rather, the initial condition of the dynamic phase error after the turn-around points (TAPs) is minimized by switching the reference phase in conjunction with one of the two methods: Firstly, a well-defined offset current is added to the charge pump output current, and its sign is switched at the TAPs. Secondly, a binary weighted loop filter capacitor array is used in the loop filter, and the total capacitance is adapted to the slope of the frequency sweep. While the first method lends itself to a fully integrated PLL design including the loop filter, the second method achieves a lower in-band phase noise.