TCAD Framework for HCD Kinetics in Low V_D Devices Spanning Full V_G/V_D Space

The time kinetics of hot carrier degradation (HCD) is modeled using a reaction diffusion drift (RDD) framework. It is incorporated into Sentaurus Device TCAD and validated using conduction mode HCD data in n- and p-channel MOSFETs and FinFETs. RDD-enabled TCAD calculates carrier-energy-initiated generation of interface traps (ΔN _IT ) and the impact of the resulting localized charges on device parametric drift. HCD at various gate (V _G ) and drain (V _D ) biases spanning various modes (V _G ≤ and > V _D ) are simulated for low stress V _D (<; 3 V). The self-heating (SH)-effect-induced temperature (T) increase is invoked for FinFETs. Data from various experiments are analyzed and a wide range of power-law time kinetics slope (n) is explained.