Low-Latency Sorter Architecture for Polar Codes Successive-Cancellation-List Decoding

2020 IEEE Workshop on Signal Processing Systems (SiPS)(2020)

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摘要
This article presents a low-latency sorting architecture for the successive-cancellation-list decoding of polar codes. Unlike previous works, this architecture is not based on a compare-and-select network and has a shorter critical path even for large list sizes. The use of known information about the input data of the module reduces the hardware complexity of the sorting module and slightly reduces the critical path. On average, the proposed architecture reduces the processing latency of « 3 χ compared to sorting networks in the literature.
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关键词
Sorting,Decoding,Measurement,Hardware,Complexity theory,Computer architecture,Adders
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