Investigation of Grain Boundaries Effect on 3D NAND Flash by TCAD Simulation

3D NAND flash memory has become a state-of-the-art technology of non-volatile memory. Different from planar 2D NAND flash memory, polysilicon channel is adopted by 3D NAND flash memory. Because of grain boundaries, device suffers from significant performance variation. This work investigates the effect of grain boundary on MONOS-structured NAND flash memory performance by TCAD simulation. The variability of electrical performance was demonstrated under random grain boundary structure. To further understand the grain boundary effect on device performance, grain size, grain boundary position and grain boundary angle was investigated. When grain size is smaller than gate length, it shows a larger threshold voltage variation. When grain size is big enough, the position of grain boundary matters. When grain boundary locates right below the middle of the gate, threshold voltage shifts the most. Moreover, comparing to vertical grain boundaries, the threshold voltage shifts up for grain boundaries in parallel to channel. This work includes a comprehensive study about the effect of grain boundary on 3D NAND flash memory performance. It could be used for the optimization of polysilicon process technology.