Optimal Architecture For Ultralow Noise Graphene Transistors At Room Temperature

The fundamental origin of low-frequency noise in graphene field effect transistors (GFETs) has been widely explored but a generic engineering strategy towards low noise GFETs is lacking. Here, we systematically study and eliminate dominant sources of electrical noise to achieve ultralow noise GFETs. We find that in edge contacted, high-quality hexagonal boron nitride (hBN) encapsulated GFETs, the inclusion of a graphite bottom gate and long (greater than or similar to 1.2 mu m) channel-contact distance significantly reduces noise as compared to global Si/SiO(2)gated devices. From the scaling of the remaining noise with channel area and its temperature dependence, we attribute this to the traps in hBN. To further screen the charge traps in hBN, we place few layers of MoS(2)between graphene and hBN, and demonstrate that the noise is as low as similar to 5.2 x 10(-9)mu m(2)Hz(-1)(corresponding to minimum Hooge parameter similar to 5.2 x 10(-6)) in GFETs at room temperature, which is an order of magnitude lower than the earlier reported values.