Predicting Power and Area for Chip Design

Chip design is an iterative and drawnout process. Each time an engineer wants an estimate of power or area for a given design, they must run logic synthesis, a procedure that takes relatively long. Our project focuses on speeding up iterations of the chip design process. The first step in our project was converting the Verilog code from behavioral to structural code and then converting this to a graph. Once we have a graph we can utilize Graph Convolutional Neural Networks to predict the area and power of a given design. We achieve our best results utilizing a Graph Convolutional Network consisting of ARMA Conv Layers. Since synthesis runtime depends on the size of a design and inference of a model has a constant runtime, we see massive benefits.