Adopting OpenCAPI for High Bandwidth Database Accelerators

Due to the scaling difficulty and high power consumption of CPUs, data center applications look for solutions to improve performance while reducing energy consumption. Among different solutions, heterogeneous architectures utilizing both CPUs and accelerators, such as FPGAs, show promising results. FPGAs have more potential to achieve high throughput, low latency and power-efficient designs compared to a general-purpose processor. However, wide adoption of FPGAs is limited by the relatively low bandwidth between the CPU and FPGA, limiting applications mainly to computationintensive problems. Meanwhile, database systems have sought ways of achieving high bandwidth access to the data. One trend here is the increasing usage of in-memory database systems. This kind of system has higher data access speed than disk-based database systems, leading to a high data processing rate. In order to leverage emerging heterogeneous architecture to accelerate the databases, we need to solve the interconnect bottleneck. A recent advancement is the introduction of the Open Coherent Accelerator Processor Interface (OpenCAPI) [1], which provides a significant increase in bandwidth compared to the current state-of-the-art (PCIe gen 3). This change requires re-evaluation of our current design methodologies for accelerators. This abstract presents our ongoing work towards a heterogeneous architecture for databases with high memory bandwidth connected FPGAs. Based on this architecture, three accelerator design examples that have promising throughput and can keep up with the increased bandwidth are proposed.