VTR 8: High Performance CAD and Customizable FPGA Architecture Modelling

Developing Field Programmable Gate Array (FPGA) architectures is challenging due to the competing requirements of different application domains, and manufacturing process technology. This is compounded by the difficulty of fairly evaluating FPGA architectural choices, which requires sophisticated high-quality Computer Aided Design (CAD) tools to target each potential architecture. This article describes version 8.0 of the open source Verilog To Routing (VTR) project, which provides such a design flow. VTR 8 expands the scope of FPGA architectures which can be modelled, allowing VTR to target and model many details of both commercial and proposed FPGA architectures. The VTR design flow also serves as a baseline for evaluating new CAD algorithms. It is therefore important, for both CAD algorithm comparisons and the validity of architectural conclusions, that VTR produce high-quality circuit implementations. VTR 8 significantly improves optimization quality (14% minimum routable channel width, 41% wirelength, and 11% critical path delay reductions), run-time (6.3x faster) and memory footprint (3.3x lower). Finally, we demonstrate VTR is run-time and memory footprint efficient, while producing circuit implementations of reasonable quality compared to highly-tuned architecture-specific industrial tools -- showing that architecture generality, good implementation quality and run-time efficiency are not mutually exclusive goals.