Hybrid Phase Modulators with Enhanced Linearity

As the CMOS technology advances, a digital-intensive design is essential for low-cost multistandard transceiver systems. The ΔΣ phase-locked loop (PLL) enables digital phase modulation without requiring digital-to-analog converters (DACs) and RF up-converters, thus significantly simplifying the overall transmitter architecture. Since the typical PLL bandwidth is not wide enough to accommodate the required modulation symbol rate, a digital compensation method [1–4] or a two-point modulation method is employed [5–15] to overcome the bandwidth limitation. In the digital compensation method, the transfer function of the digital compensation filter needs to be matched well with that of the PLL. However, the loop dynamics of the PLL is highly sensitive to process and temperature variations, making the digital compensation method less attractive for on-chip modulation. On the other hand, the two-point modulation …