Reconfiguration of Embedded Accelerators by Microprogramming for Intensive Loop Computations

The work presented in this paper is on reconfigurable accelerators for the implementation of iterative computations and loops that form the core computations of applications like those in digital signal processing and machine learning. The accelerators become computation engines of an embedded system that can be reconfigured by an embedded processor for handling various kernels of embedded applications. This paper presents our MicroProgramed Configurable Accelerator (iMPAC) architecture and compares implementing a kernel (here a matrix multiplication) on this architecture with a) a program running of an embedded processor and b) with a hardwired controller accelerator. Our prototyping on an FPGA shows very little penalty in terms of energy consumption and required clock cycles when compared with the latter, and significant improvement of both energy and timing when compared with the former. At the same time, we have the programming flexibility of the former.