Performance optimization of pixelated CdZnTe detector readout by analog ASIC using cathode waveform

Traditional analog ASICs use filtered signals passing a constant threshold to obtain the trigger time of induced signals from a pixelated CdZnTe detector. However, poor signal-to-noise ratio (SNR) and variable leading edge of the cathode signal cause higher trigger threshold and lower timing resolution. In this study, only the anode channels of analog ASICs are used to trigger the system, and the corresponding cathode waveforms are sampled by an external high-speed analog-to-digital converter (ADC). Rise time and amplitude of the cathode signal can be obtained by digital signal processing (DSP), which achieves a good timing resolution and eliminates the ballistic deficit. The test was carried out on a system with 2 x 2 detector array. The reconstructed depths are improved by using cathode waveforms, and the optimal energy resolution of 0.54% full width at half-maximum (FWHM) at 662 keV for all single-pixel events has been observed in one detector.