17.8 A 170MHz-Lock-In-Range and -253dB-FoMjitter 12-to-14.5GHz Subsampling PLL with a 150µW Frequency-Disturbance-Correcting Loop Using a Low-Power Unevenly Spaced Edge Generator.

Sub-sampling PLLs (SSPLLs) are popular for generating low-jitter output signals. However, the critical problem of SSPLLs is that they do not use a frequency divider, so the lock-in range is strictly limited. The lock-in range is defined as the maximum instantaneous disturbance at which the PLL can recover its output frequency, f OUT , to the target frequency, f TA , [1], and the lock-in range of SSPLLs generally is restricted to less than 40% of the reference frequency, f REF [2]. As shown at the top left of Fig. 17.8.1, if a sudden frequency disturbance, f D , occurring through the supply or the control voltage is within the lock-in range, it can be corrected by the PLL, allowing f OUT to be recovered as f TA . However, if f D exceeds the lock-in range, it causes lock failure or false locking. As f OUT increases, the external disturbance with the same magnitude causes a larger f D which implies that the problem of the lock-in range is more serious when we aim for a higher f OUT given f TA . Despite their popularity, conventional frequency-locked loops (FLLs) [3], [4] require large power due to dividers operating at f OUT , To save power, the FLL in [2] operates once every 200 reference cycles, but this method has a problem in that the f D -detecting time increases in inverse proportion to the duty cycle of the FLL, which increases the overall frequency re-acquisition time, f RA . Another solution is to extend the lock-in range by increasing f REF However, when a reference multiplier is used in a conventional way, it requires large power, since every edge at the output must have very low jitter [5] to avoid deteriorating the PLL output jitter. It also degrades the resolution of the f OUT of integer-N PLLs [6].