A study of optimal cost-skew tradeoff and remaining suboptimality in interconnect tree constructions

Cost and skew are among the most fundamental objectives for interconnect tree synthesis. The cost-skew tradeoff is particularly important in buffered clock tree construction, where clock subnets are an important "sweet spot" for balancing on-chip variation-aware analysis, skew, power and other factors. In advanced nodes, where both performance and power are critical to IC products, there is a renewed challenge of minimizing wirelength while controlling skew. In this work, we formulate the minimum-cost bounded skew spanning and Steiner tree problems as flow-based integer linear programs, and give the first-ever study of optimal cost-skew tradeoffs. We also assess heuristics (notably, Bounded-Skew DME (BST-DME), Steiner shallow-light tree (SALT), and Prim-Dijkstra (PD)) that are currently available for trading off cost and skew. Experimental results demonstrate that BST-DME has suboptimality ∼ 10% in cost at iso-skew and ∼ 50% in skew at iso-cost. In addition, SALT and PD shows suboptimality in terms of skew by up to ∼ 3x.