Model-Based Design of Flexible and Efficient LDPC Decoders on FPGA Devices

Advances in digital communication advocate for the use of hardware LDPC decoders in applications requiring reliable and fast information transfer. Hand-coded RTL architectures provide the highest performances but slower the path to IP design. By the use of HLS-based methodology, a number of approaches exists to facilitate development and to rapidly incorporate hardware accelerators into end-user applications. In this paper we present a generic SystemC behavioral model to generate efficient hardware LDPC decoders using Xilinx Vivado HLS. We evaluate the performance of provided architectures and assess efficiency over competing approaches. Hardware complexity reduction up to 10× are shown whereas the throughput speedups are between 1.5× and 16×. The provided architectures have performance in the same order of magnitude of handcrafted RTL architectures.