A 1.26-Ps-Fom Output-Capacitorless Ldo With Dual-Path Active-Feedback Frequency Compensation And Current-Reused Dynamic Biasing In 65-Nm Cmos Technology

An output-capacitorless low-dropout regulator (OCL-LDO) using dynamic biasing with cross-summed error current to enhance transient response has been presented in this paper. Compared to the conventional OCL-LDO with common-source differential input stage, a cross-coupled common-gate (CG) differential pair has been adopted to be the input stage of the error amplifier (EA), so that both the equivalent transconductance and the unity-gain-frequency (UGF) can be doubled. As a result, it reduces the input resistance of the EA and improves the stability of the proposed LDO. Moreover, the cross-summed error currents boost the slew rate at the gate of power transistor and further improve the transient response. The proposed OCL-LDO is designed in 65-nm CMOS technology. The input voltage range is 0.95-1.2V, and output voltage is 0.8V. It can work stably in a load range of 0-100 mA under output capacitance of 0-100 pF. A simulated Figure-of-Merit (FoM) of 1.26 ps is achieved with 13.9-mu A quiescent current only.