Circuit Models for the Inductance of Eight-Terminal Decoupling Capacitors

The series inductance associated with decoupling capacitors can contribute significantly to the impedance of the power distribution network. The eight-terminal capacitors considered in this article have a lower self-inductance than two-terminal capacitors and are commonly used in IC packages. Manufacturers typically specify the inductance of the capacitor using some type of equivalent series inductance (ESL), but this ESL may not accurately predict the inductance seen during use because it does not account for the coupling between the capacitor and nearby structures like the return plane. To adequately determine the inductance associated with an eight-terminal capacitor, models of typical eight-terminal capacitors were developed in Dassault Systèmes CST Studio Suite. The partial element equivalent circuit (PEEC) method was used to construct simple models that can be simulated in SPICE. PEEC provides analytic insight into the source of inductance. Modeling the electrode stack as a solid block rather than a multilayer structure was shown to only change the computed inductance by 3% (~1 pH) and to substantially reduce the compute time. CST and PEEC models agreed within 9% (~3 pH), demonstrating the adequacy of the simpler PEEC models. Studies of the impact of the design parameters demonstrate that the distance between the capacitor and the reference plane has the greatest influence on inductance and that the placement of vias within the pads is important.