A Fast-Transient and High-Accuracy, Adaptive-Sampling Digital LDO Using a Single-VCO-Based Edge-Racing Time Quantizer

A digital low-dropout (LDO) voltage regulator using a single-VCO-based edge-racing time quantizer (SVER TQ) was designed to achieve a fast-transient response and a high-accuracy of the output voltage. As the sampling frequency generated from the SVER TQ is scaled dynamically according to the magnitude of errors in the output voltage, its transient response can be improved without the increase in the power consumption in the steady state. For the SVER TQ, since two injected edges equally pass through all delay cells in a single VCO, the accuracy of regulation is not degraded by mismatches between the delay cells. The proposed digital LDO was fabricated in a 65-nm CMOS process, and it occupied a silicon area of 0.0488 mm ² . In measurements, the digital LDO in this letter achieved a 0.29-ps-transient FOM and a sub-2-mV accuracy under a 0.5-V supply.