Hardware Spiking Neural Networks: Slow Tasks Resilient Learning with Longer Term-Memory Bits

When aiming at efficient and low-power processing of event-based data, hardware implementations of spiking neural networks that co-integrate analog silicon neurons with memristive synaptic crossbar arrays are a promising framework. Fully analog systems however commonly make it difficult to learn patterns with real-world timescales, which are typically beyond the millisecond, due to intrinsic constraints of the underlying technologies. In this work, we propose to alleviate this issue by supplementing each presynaptic unit with a single memory bit, which allows to implement a hardware-friendly Spike Timing-Dependent Plasticity. By simulation means on the N-MNIST dataset, we illustrate the potential of this concept and show its robustness to postsynaptic neuron variability. We also discuss how to circumvent challenges raised by initial weight distribution. These results could facilitate the emergence of embedded smart systems directly fed by event-based sensors.