Evaluation of Static/Transient Performance of TFET Inverter Regarding Device Parameters Using a Compact Model

This paper seeks to address the effect of trap– assisted tunneling (TAT) and ambipolarity on the DC and transient behavior of tunnel-field effect transistors (TFETs) using a compact model. The model is implemented in Verilog–A language and presents both AC and DC characteristics of TFET. The robustness and flexibility of the numerical compact model make it possible to simulate the TFET not only as a single element but also in circuit level. Hence, it is used to simulate a TFET inverter and a 3–stage TFET ring–oscillator. In order to evaluate the impact of TAT and TFET ambipolarity, simulations are presented for different trap densities and drain doping concentrations. It is shown that the changes in flat–band voltage (V fb ) can drastically affect the performance of the TFET inverter, whereas ambipolarity and TAT nearly have no impact on the transient performance. In the end, TFET inverter delay as a function of channel length and in dependency of V fb is depicted and compared with conventional MOSFET.