An Inherently Secure FPGA using PUF Hardware-Entanglement and Side-Channel Resistant Logic in 65nm Bulk CMOS

We present an inherently secure FPGA that uses PUF-based hardware-entanglement of the configuration data and a side-channel resistant, self-timed logic style. The 3.14mm x 2.47mm testchip is fabricated in 9-metal 65nm bulk CMOS, contains the secure 10x10 tile FPGA fabric (six 6-input LUTs each), and runs at 290MHz at nominal 1V VDD and room temperature. The 38,400 PUF bits exhibit high uniqueness, randomness, and a BER < 8.1*10 ⁻¹² .