Becoming More Tolerant: Designing FPGAs for Variable Supply Voltage

With the end of Dennard scaling, FPGA power consumption has become a major concern. While FPGAs are conventionally supplied by a fixed supply voltage (Vdd), recent industrial (SmartVID) and academic solutions (dynamic voltage scaling) have shown significant power savings by scaling the FPGA Vdd on a chip-specific or chip-and application-specific basis. However, FPGAs have historically been designed for fixed-Vdd operation, which raises the question of whether we can design FPGA circuitry that is better suited for voltage scaling. In this work, we show that conventional LUTs are more sensitive to voltage than routing, so we design different LUT circuits that are more tolerant to voltage scaling. Compared to a conventional LUT, our fastest proposed LUT reduces the average critical path delay by 14% and 47% at nominal (0.8 V) Vdd and at reduced (0.6 V) Vdd, respectively. This significant reduction in delay comes at a cost of only 8% FPGA tile area increase. Our proposed LUT designs result in lower energy-delay and energy-delay^2 products at nominal Vdd and below.