Gate mapping impact on variability robustness in FinFET technology

Traditionally, complex gates are adopted to reduce area, delay and power consumption. However, they can introduce challenges related to a robustness that might be avoided with more regular and basic cell rules. This work shows the relation between gate mapping and process variability robustness in FinFET technology, exploring for the same circuit, a complex-gate design and a basic gates one. The transistor arrangement adopted can vary by up to 30% the delay robustness, around 18% the robustness to the power consumption and 25% the Power-Delay-Product deviation.