The Design Of Lightweight And Multi Parallel Cnn Accelerator Based On Fpga

In this paper, a lightweight, parallel computing and storage, high energy efficiency CNN accelerator based on FPGA was designed. According to the characteristics of forward inference structure of deep convolution neural network, the parallel characteristics of convolution operation are analyzed from two aspects of computational efficiency and data reuse rate, and the full parallel pipeline implementation of full connection layer is studied. The accelerator has adopted full parallel pipeline structure to improve the computational efficiency, and making full use of various convolution parallel computing architectures to balance the requirements of computing efficiency, parameters and data load bandwidth, a lightweight and tightly coupled accelerator architecture is designed based on the characteristics of hardware resources such as internal computing, logic and storage in FPGA. In the validation test of open data set based on ImageNet, the accelerator is deployed on Xilinx Virtex7-690T FPGA with 28nm technology, under the working frequency of 200MHz, the maximum number of multiplication and addition operation is 1728 times per cycle, the peak operation rate is 691.2Gops, the energy ratio is 138.24Gops/w. In the end, the classification results are consistent with the processing results using double-precision floating-point data format.