Analyzing the Resilience to SEUs of an Image Data Compression Core in a COTS SRAM FPGA

In this paper, we evaluate the error resilience of an image data compression IP core, an FPGA-based accelerator of the CCSDS 121.0-B-2 algorithm used to compress the ESA PROBA-3 ASPIICS Coronagraph System Payload image data. We have enhanced a fault injection platform previously proposed for the SEU evaluation of FPGA soft processor cores to interface with the target image data compression IP core and calculate the required for failure analysis image quality metrics. Through an extensive fault injection campaign, we analyze the vulnerability of the image compression core against Single Event Upsets (SEU) in a SRAM FPGA configuration memory. The soft errors are classified and evaluated depending on their effects in the operation of the compression core and the quality of the reconstructed images based on the structural similarity index metric (SSIM). The experimental fault injection results demonstrate error resiliency inherent to the image compression algorithm implementation that can be exploited to tradeoff an acceptable lossless compression performance degradation or a negligible effect on compression fidelity for significant savings in FPGA resource utilization (23% LUTs and 17% FFs) using a selective protection of the compression core modules.